Another interesting project in the latest “open” hardware movement. [http://riscv.org]. I was mainly curious to see what kind of plans they had for the ISA, and whether it deviated much from the current RISC designs we have today in the form of MIPS and AARCH32. They claim to have a plan for volume manufacturing. The real question is - who would provide the incentive for such a thing? This is the biggest problem with these sort of projects. It’s not something that happens overnight - and is largely dictated by those who hold a big pile of cash.